ENABLING A SOFTWARE DRIVEN VERIFICATION

9 Sep

DVCon-Bangalore 2015

Software driven verification and ways of achieving this are being debated under the new industry’s standards body Accellera. Any verification/validation initiative has an ultimate goal of “Catching-the-Bugs” before a tape-out. While traditional methods have resulted in various flows and methodologies, there is still a scope for achieving the intended purpose by exploring beyond the purview of traditional approach. Using a real world software, that would ultimately RUN on the semiconductor/SoC, before the SoC tape-out is a new frontier for verification teams. While model-driven (virtual platforms) design flow is one of the ways to make this happen, often the primary goal of this design methodology has been to accelerate software development in parallel to the hardware/SoC design phase. In recent times availability (and of course to some extent affordability) of emulation platforms has helped to use software for verification/validation. While this flow starts taking roots, the hardware and software teams in organisations are facing the challenge of multiple versions of software being written, tested and productised.

A recent initiative at Accellera (portable stimulus work group) is industry’s first collective step to address this challenge. The goal of this initiative is to enable a common set of high level specifications for test & validation that would enable SoC designers to seamlessly move across different stages of verification & validation across simulation, emulation and post-silicon design phases. Once a common set of specifications become available then it paves way for the traditional EDA teams/players to roll out automation tools, there by reducing the over all TIME, EFORT and COSTS involved in modern SoCs. There are two important aspects that I would like to focus on this blog. A set of high level specifications that would enable automation of test cases is one part of the solution but equally important is a layer of software that acts as an interface or “driver of test cases” to the underlying hardware. This piece of software typically represents the “programmers view of hardware” and also to some extent defines the “environment” in which the high level test cases would operate.

Vayavya labs has spent last several years in defining a high level abstractions that would allow a SoC design teams to capture the programmers views of the hardware and also the environment specific data. Once the formal specifications are available then using Vayavya’s tools, customers will be able to automate the bare metal drivers or environment specific glue-logic. The higher level system test cases either generated using a third party tool or manually written by different design teams can be easily integrated with bare-metal-driver code. The over all benefit is using a single high level spec that transcends the various SoC design flow stages and avoiding multiple teams often writing a piece of software for different environments for the same hardware(SoC).

Please join us at this years DVCon-Bangalore where Vayavya Labs’s principal architect, Karthick Gururaj, would be engaging you in an interesting panel discussion along with other industry experts, discussing how verification & validation engineers can leverage the portable stimulus across domains & disciplines.

Leave a Reply